reveal.js

# Instruction Memory and Decode

---

CS 130 // 2025-10-22

## Instruction Memory on the CPU

![Instruction Fetch](/Fall2025/CS130/assets/images/COD/instruction_fetch.png)

## Demo: Make it in Logisim

<div>
Use a ROM to simulate instruction memory

- 16 bit address (should be 32 for MIPS, but that is too big for Logisim)
- Quad output - so we can read four bytes at a time
- lowest-address byte is shown first in Logisim memory contents

</div>
<div>

![MIPS program in Logisim](../../assets/images/mips-for-logisim-rom.png)

![MIPS program in MARS](../../assets/images/mips-for-logisim-mars.png)

</div>
</div>

## Exercise

- Create a Program Counter Register which iterates through the instructions in memory

![Instruction Memory in Logisim](../../assets/images/instruction-memory-logisim.png)

## Exercise

- You can set your splitter to have custom fan-out ranges
- Make a separate pin for each instruction field (opcode, rs, rt, etc.)

<div>

![Custom Ranges for Splitter](../../assets/images/custom-splitter.png)

</div>
<div>

![R-Type format](../../assets/images/COD/r-type-instruction.png) 
![I-Type format](../../assets/images/COD/i-type-instruction.png)

</div>
</div>

## What's next?

* Use these circuits (or build your own)
    - [Logisim Register File and ALU](https://ericmanley.github.io/Fall2025/CS130/assets/RegisterFileAndALU.circ)
* Think about how you can hook up your decoded instruction to the register file and ALU so that it does the right thing for the instructions

```
addi $9, $0, 7
addi $10, $0, 8
add $8, $9, $10
```