reveal.js

# Instruction Execution Stages

---

CS 130 // 2024-10-31

## Assignment 7 Reminder

- Start with what we did last time
- [Assignment 7](../../assignments/assignment-7/): do these too 
 - `and`, `or`, `xor`, `andi`, `ori`, `xori`, `slt`, `slti`
- Extra Credit: do `lw`, `sw`, `beq`, and/or `bne`

What questions/challenges have you run into?

We mat have some work time at the end of class

# Datapath and Control Review

## Review: Datapath with Control

#### Breaking down instruction execution

- Five stages:
    1. **IF**: Instruction Fetch 
     - read it from instruction memory
    2. **ID**: Instruction Decode and Register Read
     - split instruction into parts, read register data
    3. **EX**: Execute
     - ALU calculates result 
    4. **MEM**: Memory Access
     - we haven't done this yet!
    5. **WB**: Write back
     - put new data back into a register

## Example: `addi`

```mips 
addi $8, $0, 5
```
001000 00000 01000 0000000000000101

<div>

</div>
<div>

- IF:

- ID:

- EX:

- MEM:

- WB:

</div>

## Example: `addi`

```mips 
addi $8, $0, 5
```
001000 00000 01000 0000000000000101

<div>

</div>
<div>

- **IF:** PC provides instruction address, bit pattern 001000 00000 01000 0000000000000101 read from memory
 - 4 added to PC

</div>

## Example: `addi`

```mips 
addi $8, $0, 5
```
001000 00000 01000 0000000000000101

<div>

</div>
<div>

- **ID:** instruction bit pattern split apart into opcode (001000), rs (00000), rt (01000), contant (5). Opcode goes to Control Unit. Value 0 read from register $0 indicated by rs.

</div>

## Example: `addi`

```mips 
addi $8, $0, 5
```
001000 00000 01000 0000000000000101

<div>

</div>
<div>

- **EX:** Value 0 (from $0) and 5 (from instruction constant) added together in ALU. 
 - ALUop set to "add" code
 - ALUSrc set to 1
 - Branch set to 0

</div>

## Example: `addi`

```mips 
addi $8, $0, 5
```
001000 00000 01000 0000000000000101

<div>

</div>
<div>

- **MEM:** None
 - MemRead and MemWrite both set to 0

</div>

## Example: `addi`

```mips 
addi $8, $0, 5
```
001000 00000 01000 0000000000000101

<div>

</div>
<div>

- **WB:** result from ALU (5), written to register $8 (specified by rt)
 - RegWrite set to 1
 - RegDst set to 0
 - MemtoReg set to 0
</div>

# Supporting More Instructions

## Load Instruction

Let's describe what happens for a load operation like

```mips 
lw $8, 4($9)
```

100011 01001 01000 0000000000000100

<div>

</div>
<div>

- IF:

- ID:

- EX:

- MEM:

- WB:

</div>
</div>

## Exercise: Store Instruction

Describe what happens for a store operation like

```mips 
sw $8, 4($9)
```

101011 01001 01000 0000000000000100

<div>

</div>
<div>

- IF:

- ID:

- EX:

- MEM:

- WB:

</div>
</div>

## Exercise: Branches

Describe what happens for a branch instruction like

```mips 
beq $8, $9, 5 #jump ahead 5 instructions
```

000100 01000 01001 0000000000000101

<div>

</div>
<div>

- IF:

- ID:

- EX:

- MEM:

- WB:

</div>
</div>

# Performance Issues

## Performance Issues
- Longest delay determines clock period
- 
 Some stages of the datapath are idle waiting for others to finish
- 
 Can improve performance by **pipelining**