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# Sequential Logic

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CS 130 // 2024-10-10

# Sequential Logic

## Review: Combinational VS Sequential

- A **combinational circuit** is:
    + Relies solely on the input to resolve its output
    + Stateless / memoryless / doesn't depend on previous states

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- A **sequential circuit** is:
    + Relies on input *and* current state to resolve its output
    + Has memory

## Review: S-R Latch
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<div>

- A "set reset" latch is implemented with
    <img src='/Fall2024/CS130/assets/images/COD/sr-latch.png' alt="S-R latch diagram" />
- S = 1 $\rightarrow$ change Q to 1
- R = 1 $\rightarrow$ change Q to 0
- S = R = 0 $\rightarrow$ leave Q as is

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<table>
  <tbody>
    <tr><th>$S$</th><th>$R$</th><th>$Q$</th><th>$\overline{Q}$</th><th bgcolor="lightgray"></th><th>$Q_\text{next}$</th><th>$\overline{Q}_\text{next}$</th></tr>
    <tr> <td>0</td> <td>0</td> <td>0</td><td>1</td><td bgcolor="lightgray"></td><td>0</td><td>1</td></tr>
    <tr> <td>0</td> <td>0</td> <td>1</td><td>0</td><td bgcolor="lightgray"></td><td>1</td><td>0</td></tr>
    <tr> <td>1</td> <td>0</td> <td>0</td><td>1</td><td bgcolor="lightgray"></td><td>1</td><td>0</td></tr>
    <tr> <td>1</td> <td>0</td> <td>1</td><td>0</td><td bgcolor="lightgray"></td><td>1</td><td>0</td></tr>
    <tr> <td>0</td> <td>1</td> <td>0</td><td>1</td><td bgcolor="lightgray"></td><td>0</td><td>1</td></tr>
    <tr> <td>0</td> <td>1</td> <td>1</td><td>0</td><td bgcolor="lightgray"></td><td>0</td><td>1</td></tr>
  </tbody>
</table>

</div>
</div>

## D Latch
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<div>

- A "data" latch is implemented with
    <img src='/Fall2024/CS130/assets/images/COD/d-latch.png' alt="D latch diagram" />
- Let's fill in the truth table together

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</div>
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## Clocks

- Latches are controlled by clocks that regularly trigger

![D latch](../../assets/images/COD/d-latch.png)

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![D latch clocking diagram](../../assets/images/COD/latch_clock_diagram.png)

</div>
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## Exercise

- Experiment with these in Logisim
- How can you get it to store a 1 in the latch?
- How can you get it to store a 0 in the latch?

![latch with clock](../../assets/images/latch_with_clock.png)

</div>
<div>

![write-controlled latch](../../assets/images/write_controlled_latch.png)

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## D Flip Flop

- A (falling edge-triggered) **D flip flop** can be implemented with two D latches in series 
- This configuration creates a **delay** so that the output is only changed on the **falling edge** of the clock

- a rising edge-triggered flip flop can be constructed similarly

</div>

## Registers
- A **register** is a multi-bit memory component
- Registers are commonly implemented with an array of D flip flops

## Register Files
- A **register file** consists of an array of registers that can be read and written to

![Register File Diagram](/Fall2024/CS130/assets/images/COD/register-file.png)

## Register Files
- **Reading** is implemented with multiplexers

![Register File Diagram](/Fall2024/CS130/assets/images/COD/register-file-reading.png)

## Register Files
- **Writing** is implemented with a decoder

![Register File Diagram](/Fall2024/CS130/assets/images/COD/register-file-writing.png)

## Exercise: Build a register File in Logisim

- 32 bits
- at least 4 registers

![Register File Diagram](/Fall2024/CS130/assets/images/COD/register-file.png)

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<div>

![Register File Diagram](/Fall2024/CS130/assets/images/COD/register-file-writing.png) 
![Register File Diagram](/Fall2024/CS130/assets/images/COD/register-file-reading.png)

![register file glimpse](../../assets/images/register_file_glimpse.png)

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